1. Field of the Invention
The present invention relates to a method of manufacturing an insulated gate field effect transistor (hereinafter abbreviated as "IGFET") and, particularly, to a method of manufacturing a miniaturized IGFET operable at high speed.
2. Description of Related Art
An example of a conventional fabrication method of IGFET, particularly, of a gate electrode thereof, is illustrated in FIGS. 1A to 1D.
In FIG. 1A, a thermally-oxidized silicon oxide film 12 is formed on a silicon substrate 11, on which a polycrystalline silicon (hereinafter abbreviated as "polysilicon") film 13 is formed as gate electrode material. On the polysilicon film 13, a positive photoresist 14 is formed. Then, as shown in FIG. 1B, the photoresist 14 is patterned correspondingly to a pattern of a gate electrode to be formed. Thereafter, the polysilicon film 13 is etched away using the patterned photoresist 14 as a mask to form a gate electrode 23 as shown in FIG. 1C. Then, the photoresist 14 is removed. Thereafter, as shown in FIG. 1D, impurities of opposite conductivity type to that of the silicon substrate 11 are implanted by an ion-implantation method into the substrate 11 using the gate electrode 23 as a mask to form source and drain regions 15 and 16 of the opposite conductivity type in self-aligned manner with respect to the gate electrode 23.
On the other hand, an IGFET is known in which, in order to prevent undesired punch-through phenomenon between the source region 15 and the drain region 16, an impurity region having the same conductivity type as the substrate with higher density is formed between the source and drain regions. Such IGFET can be fabricated, with the same gate electrode formation shown in FIG. 1, by the steps shown in FIGS. 2A to 2D.
First, as shown in FIG. 2A, after a gate silicon oxide film 12 is formed on a major surface of an N type single crystal silicon substrate 11 by using a thermal oxidation technique, N type impurities (e.g. phosphorus) 41 are implanted thereto by an ion implantation technique to form an N type impurity region 31 of relatively high impurity density. Thereafter, in order to control an inversion threshold voltage of the IGFET to a predetermined value, P type impurities (e.g. boron) 42 are implanted to convert a region between the N type impurity region 31 and the gate oxide film 12 into a P type, for example, impurity region 32 of a suitable net impurity density. Then, as shown in FIG. 2B, a polysilicon film 13 is deposited on the gate silicon oxide film 12 through a chemical vapour deposition (hereinafter abbreviated as "CVD") method and, then, is doped with phosphorus by diffusion to increase conductivity of this film. Then, a photoresist pattern 14 is formed thereon. Then, as shown in FIG. 2C, the polysilicon film 13 is etched using the photoresist pattern 14 as a mask, resulting in a gate electrode 23 of a predetermined size. Thereafter, as shown in FIG. 2D, the substrate is ion-implanted with P type impurities (e.g. boron) 45 using the gate electrode 23 as a mask to form a P type high impurity density region as source and drain regions 15 and 16 in a self-aligned manner with respect to the gate electrode 23.
In the conventional method of manufacturing the IGFET mentioned above, however, the relatively high impurity density region 31 formed in the semiconductor substrate 11 for restriction of punch-through phenomenon exists throughout a region in which the transistor is formed and a junction is formed between this region and a whole bottom area of the source region 15 and the drain region 16 which are of high impurity density. Therefore, junction capacitance is increased, resulting in lowering switching speed of the transistor.